14 nm is 14 nanometers. This is a reference to the width of a trace used in interconnection of areas of an large Integrated Chip chip design. A typical Core-2 CPU might use 65 nm traces and have some 800 million transistors.
Intel has a very large presence at the ISSCC 2015 in San Jose this week.
Intel at ISSCC 2015This is hard to grasp for most of us. Making stuff smaller means higher yields and higher speeds and lower cost of production. It just may be that 10 nm is the end of the road for pure silicon based transistors. (More on that later.)
It was explained that while 10nm will have more masking steps than 14nm, and the delays that bogged down 14nm coming late to market will not be present at 10nm – or at least reduced. We were told that Intel has learned that the increase in development complexity of 14nm required more internal testing stages and masking implementations was a major reason for the delay, as well as requiring sufficient yields to go ahead with the launch. As a result, Intel is improving the efficiency testing at each stage and expediting the transfer of wafers with their testing protocols in order to avoid delays. We were quoted that 10nm should be 50% faster to market than 14nm was as a result of these adjustments. So while the additional masking steps at 10nm which ultimately increases fixed costs, Intel is still quoting that their methods results in a reducing in terms of cost per transistor without needing a completely new patterning process. EUV lithography was discussed, but Intel seems to be hoping to avoid it until it is absolutely necessary, as EUV development so far has been slower to progress than expected.
About the move away from silicon:
http://arstechnica.com/gadgets/2015/02/intel-forges-ahead-to-10nm-will-move-away-from-silicon-at-7nm/Heavy reading!
