I/O Address Range - Why?

[Zaeem]

Why do we have a range of port addresses just for one type of peripheral device? What's the point of leaving black spaces in I/O map?

[DaveLembke]

I was told by my teacher 8 years ago when asking a similar question at college that this is because there are plenty of port addresses to go around, more than needed to operate, so it made no sense to bind them all tightly together, but rather have them gapped instead. But this was just a verbal answer from the teacher with no physical proof to show as to why.

[BC_Programmer]

An I/O address range "maps" device input to memory. Sort of like how in old computers you could use the built in BASIC to "poke" values directly into the Video memory; the video memory was on the video board, but it was "mapped" into addressable memory.


Memory mapped I/O (which is what the "address ranges" refer to) is a method that uses the same Address bus to handle both memory and I/O devices.

With modern versions of windows, the driver for a device has to interact with it's device (obviously) so it has to get the data it wants to send to the device to that device; generally this is done via mapped I.O; whereby both the device and the driver "agree" on an area of memory where they will communicate. The driver itself get's the appropriate address range from the OS, and the OS makes sure multiple devices aren't configured to use the same range. It won't necessarily cause problems if they do; only if you use the two devices simultaneously.

So why is it a range? Well if it wasn't, the driver could only send a single byte of information to the device at once!

[Geek-9pm]

the answer given by your teacher was a very general answer.

The answer given by your teacher was satisfactory for a quick verbal answer. Years ago hardware engineers like to use the least number of of chips required for a certain task. Sometime ago Intel has established the idea of  input and output portsbeing separate from the memory array. On the IBM PC a hardware can have over 65,000 I/O ports. The coating all  addresses would requirethe chip that accepts 16 lines. Other little bit could be saved by using an design that has much less than the total 65,000. Quite often input-output chips require four ports. It depends on what kind of device you have. Work sample one port could be the data port another port could be the status port and yet another port could be a command for and yet another port could be used to set a timer. So there you would have four ports. And by the way, from the standpoint of the hardware it's really a ports, not for ports. Both the input section in the output section are really separate parts of the device, although they share the same address.
by assigning blocks of at least four address to a device it also allows for in the future the revision or new version of the chip that would require all for work addresses.
On modern motherboards there are large scale integrated circuits to take care of all the addressing and could handle any sort of addressing scheme you could wish for. What years ago hardware engineers were concerned about using regular logic chips to the code I'll address. He could make a difference if they had used to treat or four chips do the job.
This is a quick answer and I have not edited all the content. If you get the gist of what I'm talking about. Acyclic which her teacher said was essentially true. You might also tell him that I said many current I/O chips actually require four ports.

[patio]

I like BC's reply better...

[Geek-9pm]

An I/O address range "maps" device input to memory. Sort of like how in old computers you could use the built in BASIC to "poke" values directly into the Video memory; the video memory was on the video board, but it was "mapped" into addressable memory.
Memory mapped I/O (which is what the "address ranges" refer to) is a method that uses the same Address bus to handle both memory and I/O devices.

That may cause confusion. The term Memory mapped I/O generally refers to the method used my Motorola, not Intel. Apple built machines that used Memory mapped I/O .
The I/O array does not cut into space in the Memory area.

Please see this reference: 
http://www.pcguide.com/ref/mbsys/res/ioSummary-c.html

[patio]

And where does it state that this is a Motorola method that Intel does not use ? ?
You need to start qualifying your broad over-generalisations hers...

That's what causes more confusion than anything...

PS. Noone mentioned Apple...who cares how they choose to do it.

[Geek-9pm]

And where does it state that this is a Motorola method that Intel does not use ? ?
You need to start qualifying your broad over-generalisations hers...
That's what causes more confusion than anything...
PS. Noone mentioned Apple...who cares how they choose to do it.

Sperry that my first post was not edited.

Until recently, Apple used Motorola chips, not  Intel.

The 68000 had many high-end design wins early on. It became the dominant CPU for Unix based workstations including Sun workstations and Apollo/Domain workstations, found its way into heralded computers such as the Amiga, Atari ST, Apple Lisa and Macintosh, and was used in the first generation of desktop laser printers including the original Apple Inc. LaserWriter and the HP LaserJet.

Intel does NOT use memory map I/O. The specific I/O instructions are for port mapped devices.

Port-mapped I/O uses a special class of CPU instructions specifically for performing I/O. This is generally found on Intel microprocessors, specifically the IN and OUT instructions which can read and write one to four bytes (outb, outw, outl) to an I/O device. I/O devices have a separate address space from general memory, either accomplished by an extra "I/O" pin on the CPU's physical interface, or an entire bus dedicated to I/O. Because the address space for I/O is isolated from that for main memory,

The above are from the Wikipedia. Look for 'memory map I/O'

Intel instruction set for the x86 CPUs.
http://home.comcast.net/~fbui/intel.html

Motorola Instruction set for 68000.
http://en.wikipedia.org/wiki/Motorola_68000

It seems that others are confused by this. I just assume everybody knew the historical use of the term. Here is one user's confusion:
http://stackoverflow.com/questions/3194139/x86-memory-and-i-o-map

Of course, it you want to, you can build a memory map I/O thing for a PC. Most devices use port map instead of memory map.

A separate array for slower devices is a feature of the Intel design.  As yet, it is not  not used to its full potential.

BC, Please read the x86 instruction set from cover to cover.
EDIT:
Microprocessors and microcomputer-based system design - Google Books Result

Intel microprocessors can use either standard or memory- mapped I/O while Motorola microprocessors use only memory-mapped I/O
http://books.google.com/books?id=s2KPvKCQm7sC&pg=PA26&lpg=PA26&dq=motorola+uses+memory+mapped+I/O&source=bl&ots=1UOcX_Te2V&sig=j0zGN-aG11Y20I_AJ-xIe2PSthU&hl=en&ei=ktUGTbfKE4a2sAOJyPGKBw&sa=X&oi=book_result&ct=result&resnum=1&ved=0CBoQ6AEwAA#v=onepage&q=motorola%20uses%20memory%20mapped%20I%2FO&f=false

[BC_Programmer]

That may cause confusion. The term Memory mapped I/O generally refers to the method used my Motorola, not Intel. Apple built machines that used Memory mapped I/O .

the IBM PC uses memory mapped IO as well.

The I/O array does not cut into space in the Memory area.

I never said it did. In fact I'm not sure if you're talking about I/O ports, or I/O addresses, since it's rather vague. I'm not sure if it does anymore (things are probably different in protected mode and  x64 Native mode ) Although it does "use" memory in Real Mode; the 384K of HMA memory above the DOS accessible 640K was addressable by even the original IBM PC; it was reserved however to perform memory mapped I/O with the various hardware devices, as well as map the various ROM codes into addressable memory space, so that they could, you know, be executed.  Additionally, if what you say is true, I've witnessed magic when using the original PC [GW]BASIC[A] "POKE" instruction to write values to memory would light up pixels/characters on the display. I am curious how this mapping took place if there was no mapping. This was using POKE to poke memory addresses, not OUT to work with I/O Ports directly.

Today the memory doesn't stay "used"; the device driver locks an area of memory using appropriate kernel functions and communicates with the device using that memory, and then when it's finished communicating with it it unlocks it, which means the OS is free to use it for what it pleases. Bear in mind however that almost no Device nowadays really uses I/O addresses in this manner; generally the communication is handled by DMA transfers by the chipset, which manages all the hairy stuff. In fact I/O memory mapping like this is only done if you purposely force Programmed I/O on your devices; usually it's slower but if your hardware is finicky can be more reliable then DMA bus mastering.

I/O Ports are not necessarily I/O addresses, and I/O ports do not necessarily correspond directly to the electronic input into a chip or chipset.


From the same wikipedia article you quoted:

A final reason that memory-mapped I/O is preferred in x86-based architectures is that the instructions that perform port-based I/O are limited to one or two registers: EAX, AX, and AL are the only registers that data can be moved in to or out of, and either a byte-sized immediate value in the instruction or a value in register DX determines which port is the source or destination port of the transfer[1][2]. Since any general purpose register can send or receive data to or from memory and memory-mapped I/O, memory-mapped I/O uses less instructions and can run faster than port I/O. AMD did not extend the port I/O instructions when defining the x86-64 architecture to support 64-bit ports, so 64-bit transfers cannot be performed using port I/O[3].

and

Memory-mapped I/O is the cause of memory barriers in older generations of computers – the 640 KiB barrier is due to the IBM PC placing the Upper Memory Area in the 640–1024 KiB range (of its 20-bit memory addressing), while the 3 GB barrier is due to similar memory-mapping in 32-bit architectures in the 3–4 GB range.

If they didn't do memory mapped I/O, I'd like to know how they caused these observable barriers and how they would be preferable. thx.


also:

http://duartes.org/gustavo/blog/post/motherboard-chipsets-memory-map

Physical memory addresses are also used for communication with assorted devices on the motherboard (this communication is called memory-mapped I/O). These devices include video cards, most PCI cards (say, a scanner or SCSI card), and also the flash memory that stores the BIOS.

BC, Please read the x86 instruction set from cover to cover.

haha, yeah, I should read it. k.

[Geek-9pm]

Yes, read it!

To clarify.
Intel CPU have specific I/O constructionist write to the I/O array.

There is a wire, a pin on the original 8086 CPU that indicates there is an I/O operation. In general, I/O operations in the Intel universe means any operation using the specific IN and OUT instructions.Not memory references.

An engineer who built a memory map I/O for an Intel CPU may live to regret it. The dubious advantage is offset by other issues. But there has not been universal agreement on the point. But the ones who use memory-map do not wear a suit and tie. They are rebels. The rest of us are quite proper and only use the I/O map. I never used a memory map U/O in any of my designs. And I don't PEKK and POKE, I do INP and OUT, the way Intel meant it to be.

Read the Intel documentation

The floppy controller, the HDD controller, the system timer, the keyboard, the mouse and the printer port and both serial ports are devices that have a specific range of address in the I/O map. They are address, but the proper terminology is not to refer to them as memory.
Please refer to the first reference. It is an I/O port map.

There are NOT memory locations.
Thane are ports. That is  P O R T S    - to make sure I splet it write.

http://en.wikipedia.org/wiki/Input/Output_Base_Address

[BC_Programmer]

*insert Facepalm demotivator*