I need a minimum 1 clock cycle pulse on a register whenever any of a few variables (other registers) change.
The following code is in Verilog:
reg pulse;
reg [2:0] count = 0; //Count to ensure that a full clock cycle has passed
always @ (var1, var2, var3)
pulse = 1;
always @ (posedge clk) begin
if (pulse == 1)
count = count + 1;
if (count > 1) begin
pulse = 0;
count = 0;
end
end
That above results in the second Always block being ignored during synthesis optimizations.
Anyone know of a way to achieve a pulse?