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Author Topic: How do I create a pulse triggered by changes in a variable in FPGA?  (Read 3375 times)

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kokowang5699

    Topic Starter


    Rookie

    • Experience: Experienced
    • OS: Other
    I need a minimum 1 clock cycle pulse on a register whenever any of a few variables (other registers) change.
    The following code is in Verilog:
    Code: [Select]
    reg pulse;
    reg [2:0] count = 0;  //Count to ensure that a full clock cycle has passed
    always @ (var1, var2, var3)
        pulse = 1;

    always @ (posedge clk) begin
        if (pulse == 1)
             count = count + 1;
        if (count > 1) begin
             pulse = 0;
             count = 0;
        end
    end
    That above results in the second Always block being ignored during synthesis optimizations.
    Anyone know of a way to achieve a pulse?