A pipeline flush, is also known as a pipeline break or a pipeline stall. It's a procedure enacted by a CPU when it is unable to ensure that it will correctly process its instruction pipeline in the next clock cycle.
How does it work?
For any given instruction that the CPU must process, there are multiple stages of processing, called instruction or machine cycles. These stages include fetching the instruction from memory, as well as decoding and executing the commands. CPUs pipeline their instructions, which means multiple instructions can be in different stages of the machine cycle at any given time.
A hazard condition may present itself if, for instance, if two pending instructions are "data-dependent" (they depend upon or modify the same set of data in memory). In such a case, the CPU may need to clear (or "flush") the instruction pipeline to ensure that the calculations are not corrupted by the pipelining process.